SECTION 01 / 5

From SOP to a Circuit — Two-Level Logic

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Start here Last week you turned a truth table into a Sum of Products formula. This week you turn that formula into a real circuit you could build on a breadboard. The good news: every SOP becomes the same simple shape, a row of AND gates feeding one OR gate.

Quick recap: Σ notation

Number the rows of the truth table 0, 1, 2… (the row’s binary value). Then just list the rows where F=1F = 1:

F(A,B,C)=Σm(3,4,5,6,7)F \left(A , B , C\right) = \Sigma m \left(3 , 4 , 5 , 6 , 7\right) = m3+m4+m5+m6+m7m_{3} + m_{4} + m_{5} + m_{6} + m_{7}

Order matters! Σm(…)\Sigma m \left(\ldots \right) only makes sense if everyone agrees which variable is the left bit. F(A, B, C) means A is the left (biggest) bit. Always keep the variables in the order given.

SOP → circuit: the recipe

Inverters make the barred letters, each AND gate makes one minterm, and one OR gate joins them.
Inverters make the barred letters, each AND gate makes one minterm, and one OR gate joins them.
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SOP as a two-level circuit
  1. Put a NOT gate on any input that appears with a bar.
  2. Make one AND gate per product term.
  3. Feed all AND outputs into one OR gate.

This is called two-level logic (level 1: AND, level 2: OR; the NOT gates don’t count as a level).

Example: Y=A‾B‾C‾+AB‾C‾+AB‾CY = \overline{A} \overline{B} \overline{C} + A \overline{B} \overline{C} + A \overline{B} C needs 3 NOT gates, 3 three-input AND gates and 1 three-input OR gate.

Canonical is NOT minimal

The canonical SOP (all minterms) is correct but often wasteful.

Form Formula for Σm(3,4,5,6,7)\Sigma m \left(3 , 4 , 5 , 6 , 7\right) Gates needed
Canonical SOP A‾BC+AB‾C‾+AB‾C+ABC‾+ABC\overline{A} B C + A \overline{B} \overline{C} + A \overline{B} C + A B \overline{C} + A B C 5 ANDs (3-input) + 1 OR (5-input) + NOTs
Minimal SOP A+BCA + B C 1AND⁡+1OR⁡1 \operatorname{AND} + 1 \operatorname{OR}

Both give the same truth table. Finding the small one is called logic minimisation. You’ll do it with Boolean algebra now, and with K-maps in Week 5.

Check: A+BCA + B C is 1 when A=1A = 1 (rows 4–7) or when B=C=1B = C = 1 (rows 3 and 7). That’s rows 3, 4, 5, 6, 7 ✓.

In one line: Any SOP becomes a two-level circuit (NOTs → ANDs → one OR), but the canonical form is usually much bigger than the minimal one. Exam words: Σm\Sigma m notation, variable order, two-level logic, AND-OR circuit, canonical vs minimal, logic minimisation.


Quick check

F(A,B)=Σm(1,2)F \left(A , B\right) = \Sigma m \left(1 , 2\right). Which rows are these, and what’s F? 01 and 10→F=A‾B+AB‾(XOR⁡)1 0 \to F = \overline{A} B + A \overline{B} \left(\operatorname{XOR}\right).
How many AND gates does a canonical SOP with 5 minterms need? 5 (one per minterm).
Is the canonical form always the smallest? No. “Canonical ≠ minimal”: it’s a standard form, usually not the smallest.
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